The present invention relates to computer architectures and in particular to a memory cache system reducing the burden of cache coherence message transmission.
Computer processors may have cache memories which serve to reduce the processing delay associated with waiting for data from a main memory. Data expected to be used by the processor in executing a program is loaded into the cache memories. The architecture and proximity to the processor of the cache memory provide faster data access to the processor when the data is needed.
Cache coherence protocols are used when multiple processors and caches may access a common main memory. These cache coherence protocols coordinate changes in the data in individual caches (for example caused by one processor writing to its cache memory) so that the data accessed by the different processors is practically consistent. One common cache coherence protocol is the MSI coherence protocol in which the data of the cache is given a status of modified, shared, or invalid.
Generally, under such cache coherence protocols, when a given processor writes data to its cache, an invalidation message is communicated to the other caches to inform them that the corresponding data in their caches is no longer valid. The process of coordinating caches may be effected through a directory which receives and transmits coordination messages between the individual caches.
In complex multiprocessor systems, invalidation messages place severe demands on the bandwidth of inter-cache communication channels. The transmission of these messages can also represent a significant amount of energy consumption and generated heat.